A conventional Field Effect Transistor has a channel whose resistance is a function of the gate voltage. Conventional Field Effect transistors have a semiconductor channel with one end labeled the source and the second end labeled the drain. In addition, Field Effect transistors have a gate whose voltage controls the resistance of the channel. Current flowing through the channel is therefore a function of the gate voltage. The gate voltage controls the resistance by creating a depletion region across the channel. In the depletion region, there are no majority carriers; just minority carriers. The width of the depletion region along the channel is a function of the gate voltage.
Under normal operation a voltage is applied to the gate here-to-for referred to as the gate voltage, which is comprised of an RF signal and a DC bias voltage here-to-for referred to as the bias voltage. Said bias voltage is used to set the average value of the gate voltage.
FETs include but are not limited to JFET, n-type JFET, p-type JFET, MOSFET, NMOSFET, PMOSFET NMOSFET, MNOSFET, DIGMOSFET, HIGFET, TFET, HEMPT, MESFET, and the CMOSFET in the enhancement mode and in the depletion mode.
FIG. 1A illustrates a Junction Field Effect Transistor (JFET) according to prior art. It shows as an example a schematic of an idealized n-type JFET fabricated by the standard epitaxial process. The active region of the device consists of a lightly doped n-type channel 10 sandwiched between a highly doped p+ region 12 and a highly doped p+ region 14. A gate terminal 18 is connected to a metal gate electrode 20 which makes electrical contact with the p+ region 14. The p+ region 14 forms a p-n junction with the lightly doped n-type channel 10. The highly doped p+ region 12 makes electrical contact with a metal back electrode 16. A source terminal 22 is connected to a metal source electrode 24 which makes electrical contact with the n-type channel 10. A drain terminal 26 is connected to a metal drain electrode 28, which makes electrical contact with the n-type channel 10.
Within the n-type JFET during normal operations the gate is biased with a negative voltage. In particular, a p-n junction is back biased when the p side is negative with respect to the n side of the junction. A negative voltage on the gate terminal 18 back-biases the p-n junction comprised of the p+ region 14 and the lightly doped n-type channel 10. Back-biasing this junction creates a depletion region whose width is a function of the negative voltage applied to the gate terminal 18. Thus, varying the negative voltage on the gate terminal 18 changes the width of the depletion region, which causes the resistance of the lightly doped n-type channel 10 to vary. A positive voltage in the lightly doped n-type channel 10, will also back-bias the p-n junction comprised of the p+ region 14 and the lightly doped n-type channel 10.
FIG. 1B shows the voltage distribution along the lightly doped n-type channel 10 for the JFET shown in FIG. 1A, when a positive direct current (DC) voltage is applied to the drain terminal 26 by a seven-volt battery 30 and the source terminal 22 and the metal back electrode 16 are connected to ground. The voltage in the lightly doped n-type channel 10 due to the seven volts drain voltage back-biases the p-n junction which is comprised of the p+ region 14 and the lightly doped n-type channel 10. This back-bias is greatest at the drain, where the voltage in the lightly doped n-type channel 10 is seven volts at the drain and is least at the source where the voltage in the lightly doped n-type channel 10 is zero volts. The voltage drops from the metal source electrode 24 to the start of the depletion region and the voltage drop from the metal drain electrode 28 to the end of the depletion region have been neglected to simplify this discussion.
The back bias, due to the drain voltage, causes a depletion region along the channel. In the depletion region the majority carriers, electrons in the case of the n-type JFET, are removed and only minority carriers remain. The larger the back-bias the greater will be the width of the depletion region and therefore, the higher the resistance of the channel. Thus, the width of the depletion region and therefore, the resistance of the channel will be greatest at the drain and will be smallest at the source. The change in voltage per unit length in the lightly doped n-type channel 10 varies, as shown in FIG. 1B, since the resistance of the channel varies due to the variation of the width of the depletion region.
The drain voltage that causes the lightly doped n-type channel 10 in FIG. 1A to be completely depleted just at the drain is defined as VDsat and this condition is called pinch-off. FIG. 1C shows the depletion region 36 for the JFET shown in FIG. 1A when a battery 32 whose voltage is equal to VDsat is connected to drain terminal 26 and the source terminal 22 and the metal back electrode 16 are grounded. The pinch-off point is defined as the point at which pinch-off occurs closest to the source. The pinch-off point 40, is shown in FIG. 1C for the case where the drain voltage equals VDsat.
If the drain voltage is increased by ΔV the pinch-off point moves towards the source a distance ΔL to a new position 42. FIG. 1D shows the depletion region 36 for the JFET shown in FIG. 1A when a battery 34 whose voltage is equal to VDsat+ΔV is connected to drain terminal 26 and the source terminal 22 and the metal back electrode 16 are grounded. The depletion region 36 is enlarged so that over a region of length ΔL from the pinch-off point 42 to the end of the depletion region 44, the channel is completely depleted. Because only minority carriers remain, the resistance is very large. The drain current flows through this depleted region of length ΔL resulting in large losses in this high resistance region. These losses reduce the efficiency of the JFET. When the drain voltage is greater than VDsat the drain current saturates; the drain current does not increase with increased drain voltage.
FIG. 2 shows an n-type enhancement mode MOSFET according to prior art. It consists of a lightly doped p-type semiconductor 90 which makes electrical contact with a metal back electrode 108. A gate terminal 92 is connected to a metal gate electrode 94. A thin insulating layer 96 insulates the metal gate electrode 94 from the lightly doped p-type semiconductor 90. A source terminal 98 is connected to a metal source electrode 99 which makes electrical contact with a source highly doped n+ island 100. The source highly doped n+ island 100 makes electrical contact with the lightly doped p-type semiconductor 90 forming a p-n junction. A drain terminal 102 is connected to a metal drain electrode 104 which makes electrical contact with a drain highly doped n+ island 106. The drain highly doped n+ island 106 makes electrical contact with the lightly doped p-type semiconductor 90 forming a p-n junction. The purpose of said p-n junctions is to restrict the drain current to flow from said source end of the channel to said drain end of said channel.
An n-type enhancement mode MOSFET must be biased by a positive gate voltage. The metal gate electrode 94, the thin insulating layer 96 and the lightly doped p-type semiconductor 90 together form an n-type MOS capacitor. When a sufficiently large positive voltage is applied to the gate electrode 92, electrons start to accumulate in the lightly doped p-type semiconductor 90 at its interface with insulating layer 96, forming a channel from source to drain. Increasing the gate voltage attracts more electrons to this channel thereby reducing the resistance of the channel. A positive DC drain voltage applied to the drain terminal 102 creates a voltage distribution in the lightly doped p-type semiconductor 90 similar to that shown in FIG. 1B for the JFET. This voltage reduces the effect of the gate voltage reducing the number of electrons in the channel. The drain voltage applied to terminal 102 in FIG. 2, which causes the channel to be completely depleted of electrons just at the drain is defined as VDsat and this condition is called pinch-off. The pinch-off point is defined as the point at which pinch-off first occurs. If the drain voltage is increased by ΔV, the pinch-off point moves towards the source a distance ΔL as in the JFET. Over the region of length ΔL, the channel is completely devoid of electrons and therefore, the resistance is very large. The drain current flows through this region resulting in large losses. These losses reduce the efficiency of the MOSFET.
In prior art for all FETs, when a voltage VDsat is applied from the drain to the source in all FETs the channel will pinch-off causing a loss in efficiency.